1. Field of the Invention
This invention relates to a method for producing an electrically erasable and programmable read-only memory (EEPROM) device having a split-gate.
2. Technical Background
EEPROM devices are well known and widely used in a variety of electronic equipment where memory is needed that will survive an interruption of electric current. Conventional EEPROM devices have memory cells which comprise floating-gate transistors. Such devices are able to maintain information written into the memory cells in the absence of a power source for the device, and are fixer capable of having information stored in their memory cells erased. These memory devices, however, suffer from their relatively slow read/write access times, which are typically in the range of 150 to 200 nsec. EEPROM devices capable of operating at faster speeds have been developed in the last several years.
One of the problems that EEPROM devices suffer from is the problem of "over-erasure" of the memory cell contents during erasure operations. As can be seen in FIG. 1, the floating-gate transistor has a floating gate 10 and a control gate 12, capable of injecting electrons from the drain 16, based on a phenomena known as the Fowler-Nordheim Tunneling Effect, through a tunneling oxide layer 14 into the floating gate 10. The threshold voltage of a floating-gate transistor can be raised by means of such electron injection, and the device then assumes a first state that reflects the content of the memory cell. On the other hand, during erasure of the memory cell, electrons are expelled from the source 18 through the tunneling oxide layer 14 and out of the floating gate 10 of the transistor. As a result of this electron removal, the threshold voltage is lowered and thus the device then assumes a second memory state.
During the process of memory content erasure, however, to ensure complete removal of the electrons previously injected, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e. more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the floating-gate transistor becomes a depletion transistor, which conducts even in the absence of the application of a control voltage at the control gate 12. This phenomena is known in the art as memory over-erasure.
To overcome the above described memory over-erasure problem of conventional EEPROM devices, a split-gate EEPROM was proposed. In FIG. 2 schematically shows such a split-gate device. The memory device has a floating-gate transistor, which similarly includes a floating gate 20 and a control gate 22, as in the case of the floating-gate transistor of FIG. 1. However, the floating gate 20 only covers a portion of channel region and the rest of the channel region is directly controlled by the control gate 22. This split-gate based memory cell is equivalent to a series connected floating-gate transistor 33 and a enhanced isolation 35, as is schematically represented in FIG. 3. The principal advantage of such this configuration is obvious. The isolation transistor 35 is free from the influence of the state of the floating gate 20 and remains in its off state, even if the floating-gate transistor 33 is subjected to the phenomena of over-erasure and therefore is in a conductive state. The memory cell can thus maintain its correct state, which reflects the correct state of the memory contents, in spite of the over-erasure problem.
The fabrication of EEPROM devices, particularly when they are highly microminiturized, remains difficult. The dimensions of the various elements are very small which may cause misalignment difficulties.